As depicted in FIG. 1, a conventional bond pad structure 100 is built on a silicon substrate 110 covered by an oxide layer 120. The bond pad 130 is embedded within a passivation layer 140. A conductive gold wire (160) ball (150) bond is formed and attached on a central upper surface of the bond pad 130.
A disadvantage of direct bond pad connection on the top side of the die, as depicted in FIG. 1, includes the fact that they sometimes require a wire bond 160 to be electrically connected to a lead frame or other structure for final die packaging. Another method that involves flip chip packaging at the wafer level involves a re-distribution layer (RDL) that allows the bond pad pitch to be routed to a more useable pitch in order to attach a solder ball directly on the top side of the die. Both of these packaging approaches involve contacting the bond pads on the top side of the die. As a result, this limits the ability to stack memory and imager devices. Furthermore, the ability to attach the cover glass on imager wafers at the wafer level is limited due to the requirement to make contact to the bond pad on the top side of the wafer. Accordingly, it is desirable to develop a through-wafer interconnect to eliminate the need for wire bonding, to increase the volumetric circuit device density, to minimize the size of the die's packaging, to make memory devices stackable and to enable wafer level packaging (WLP) methods for imager wafers.